The quest of the HPC community for an exascale architecture created and rekindled many challenges for both hardware and software designers. Not only have new problems emerged (stricter energy constraints, heterogeneous architectures, …), but also time-proven solutions to old problems (distributed checkpointing, routing algorithms, …) have been pushed to their limit. This enticing topic sets the stage for this panel in which these challenges and the opportunities they create will be discussed. Moderated by Mateo Valero (Barcelona Supercomputing Center), three specialists will describe and discuss their insights into this exciting moment we live at the brink of exascale computing.

Panel Members

Jean-Luc Gaudiot UC Irvine, USA

Jean-Luc Gaudiot received the Diplôme d’Ingénieur from ESIEE, Paris, France in 1976 and the M.S. and Ph.D. degrees in Computer Science from UCLA in 1977 and 1982, respectively. He is currently Professor in the Electrical Engineering and Computer Science Department at UC, Irvine. Prior to joining UCI in 2002, he was Professor of Electrical Engineering at the University of Southern California since 1982. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 250 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as a number of industrial companies. He has served the community in various positions and was just elected to the presidency of the IEEE Computer Society for 2017.

Lawrence Rauchwerger Texas A&M University, USA

Lawrence Rauchwerger is the Eppright Professor of Computer Science and Engineering at Texas A&M University and the co-Director of the Parasol Lab. He received an Engineer degree from the Polytechnic Institute Bucharest, a M.S. in Electrical Engineering from Stanford University and a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. He has held Visiting Faculty positions at the University of Illinois,
Bell Labs, IBM T.J. Watson, and INRIA, Paris.

Rauchwerger’s approach to auto-parallelization, thread-level speculation and parallel code development has influenced industrial products at corporations such as IBM, Intel and Sun. Rauchwerger is an IEEE Fellow, an NSF CAREER award recipient and has chaired various IEEE and ACM conferences, most recently serving as Program Chair of PACT 2016 and PPoPP 2017.

Yale Patt The University of Texas at Austin, USA

Yale Patt is a teacher at the local public university in Austin, Texas. He enjoys teaching the intensive required intro to computing course to 400 freshmen every other Fall, the advanced graduate course in microarchitecture every other Spring, and the senior-level computer architecture course whenever they let him. He also enjoys his visits to Brazil, and participating from time to time in SBAC, Brazil’s increasingly important computer conference. Dr. Patt has earned appropriate degrees from reputable universities and has received more than enough awards for his research and teaching. More detail can be found on his website.

Per Stenstrom Chalmers University of Technology

Per Stenstrom (Chalmers University of Technology) is a professor of computer engineering at Chalmers University of Technology since 1995 where I teach and manage a research program in computer architecture. I’m also interested in the interplay between research and innovation processes. To this end, I am on the board of Chalmers Innovation and involved in a number of initiatives to promote entrepreneurship. I am also working on the establishment of EuReCCA - a pan-European virtual center in Computer Systems Architecture. Before coming to Chalmers I was on the faculty of Lund University where I received my MSc in Electrical Engineering and Ph D in Computer Engineering. My research program centers on computer architecture with a current research emphasis on design principles for chip multiprocessors (or multicores as many refer to them). My publications in the past include more than a hundred published papers and three textbooks. I have been a visiting scientist at Carnegie Mellon University (1987-1988), Stanford University (1991), and University of Southern California (1993) and in 2003, I spent a sabbatical leave at Sun Microsystems. I’m Associate Editor-in-Chief of Journal of Parallel and Distributed Computing and Senior Associate Editor of ACM Transactions on Architecture and Code Optimization (TACO). I am regularly serving program committees for computer architecture and parallel processing conferences. I have also acted as program and general chair for a number of conferences. I was general chair of the 28th Annual International Symposium on Computer Architecture (ISCA) in 2001 and program chair of the same symposium in 2004. In 2008 I was program co-chair of the IEEE International Symposium on High-Performance Computer Architecture (HPCA) held in Salt Lake City and in 2009 I was the program chair for the IEEE IPDPS held in Rome. I am a co-founder of the International Conference on High-Performance and Embedded Architectures and Compilers and acted as its general co-chair in 2008 and program co-chair for the same in 2007 and am now Steering Committee chair for this conference series. I am also spending a considerable amount of time as a co-founding partner of the HiPEAC network. I’m a Fellow of the IEEE and a member of the IEEE Computer Society. I am also a Fellow of the ACM, and member of SIGARCH. Since 2009 I am a member of the Royal Swedish Academy of Engineering Sciences and since 2010 of the Academia Europaea.